1. Field of the Invention
The present invention generally relates to a package substrate, and more specifically to a package substrate for a high density package.
2. Description of the Prior Art
Miniaturization of electronic products is an inevitable trend in this modern world. Accordingly, semiconductor chips and package substrates for the chips have changed in their dimensions for meeting the requirements of low-profile, compact electronic products. Nowadays, the circuit density of the semiconductor chip has become higher and higher as well as the pin count thereof, and pitches between conductive pads of the semiconductor chip have been reduced to nanoscale. However, pitches between pads of a traditional flip-chip package substrate are only at around a hundred micron. Accordingly, the traditional flip-chip package substrate may not be applicable to a semiconductor chip with a high circuit density and a high pin count. Furthermore, in a thermal cycling reliability testing procedure, there exists a large coefficient of thermal expansion (CTE) difference between the semiconductor chip and the traditional flip-chip package substrate. This causes an uneven thermal stress and may destroy the connection between the package substrate and the chip, thereby decreasing the reliability and product yield.
U.S. Pat. No. 8,269,337 discloses a package substrate. FIG. 1 depicts a cross-sectional view showing an application of the package substrate. The package substrate includes an interposer 212, a redistribution-layer structure 213, a build-up structure 24, a molding layer 22, and a semiconductor chip 27. A redistribution structure 21 is consisted of the interposer 212 and the redistribution-layer structure 213. The interposer 212 is made of glass, silicon, ceramic, or polymer. As shown in FIG. 1, the interposer 212 has a plurality of through-silicon vias (TSVs) 210 penetrating the bottom surface thereof. The redistribution-layer structure 213 is formed on the top surface of the interposer 212. The innermost circuit of the redistribution-layer structure 213 is electrically connected to the top ends of the TSVs 210, and the outer most circuit of the redistribution-layer structure 213 has a plurality of electrode pads 211. The redistribution structure 21 is embedded in the molding layer 22. The build-up structure 24 is formed on the bottom surface of the molding layer 22. The build-up structure 24 has a plurality of conductive vias 242, a portion of which are electrically connected to the bottom ends of the TSVs 210 of the interposer 212. The semiconductor chip 27 is a flip-chip electrically connected to the electrode pads 211 of the redistribution-layer structure 213 through solder bumps 271, and an underfill material 270 is used to fill the space between the electrode pads 211 and the semiconductor chip 27. A plurality of solder balls 26 are mounted on bonding pads 243 on the bottom side of the build-up structure 24, for being electrically connected to another electronic device such as a printed circuit board (not shown in the figure).
By deploying the redistribution structure 21, the package substrate can overcome the dimension mismatch between the semiconductor chip 27 and the printed circuit board. The semiconductor chip 27 with high-density or small-pitch conductive pads 272 can be disposed on the printed circuit board through the package substrate. Furthermore, the interposer 212 serves as a CTE buffer between the semiconductor chip 27 and the printed circuit board. Therefore, during thermal cycling reliability testing procedure, uneven thermal stress caused in the package substrate may be reduced. This makes the structure of the package substrate more reliable.
However, a great CTE difference may exist since the CTE of the interposer 212 is about 3 ppm/K and the CTE of the molding layer 22 and dielectric layers of the build-up layer 24 is about 5 to 15 ppm/K. Therefore, a great inner stress may occur in the embedded redistribution structure 21 and cause the cracking and failure of the redistribution structure 21.
Therefore, there is a need to provide a package substrate for overcoming the above-mentioned disadvantages in the prior art.